library verilog;
use verilog.vl_types.all;
entity pmi_pll_fp is
    generic(
        pmi_freq_clki   : string  := "100.0";
        pmi_freq_clkfb  : string  := "100.0";
        pmi_freq_clkop  : string  := "100.0";
        pmi_freq_clkos  : string  := "100.0";
        pmi_freq_clkok  : string  := "50.0";
        pmi_family      : string  := "EC";
        pmi_phase_adj   : string  := "0.0";
        pmi_duty_cycle  : string  := "50.0";
        pmi_clkfb_source: string  := "CLKOP";
        pmi_fdel        : string  := "off";
        pmi_fdel_val    : integer := 0;
        module_type     : string  := "pmi_pll_fp"
    );
    port(
        CLKI            : in     vl_logic;
        CLKFB           : in     vl_logic;
        RESET           : in     vl_logic;
        CLKOP           : out    vl_logic;
        CLKOS           : out    vl_logic;
        CLKOK           : out    vl_logic;
        CLKOK2          : out    vl_logic;
        LOCK            : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_freq_clki : constant is 1;
    attribute mti_svvh_generic_type of pmi_freq_clkfb : constant is 1;
    attribute mti_svvh_generic_type of pmi_freq_clkop : constant is 1;
    attribute mti_svvh_generic_type of pmi_freq_clkos : constant is 1;
    attribute mti_svvh_generic_type of pmi_freq_clkok : constant is 1;
    attribute mti_svvh_generic_type of pmi_family : constant is 1;
    attribute mti_svvh_generic_type of pmi_phase_adj : constant is 1;
    attribute mti_svvh_generic_type of pmi_duty_cycle : constant is 1;
    attribute mti_svvh_generic_type of pmi_clkfb_source : constant is 1;
    attribute mti_svvh_generic_type of pmi_fdel : constant is 1;
    attribute mti_svvh_generic_type of pmi_fdel_val : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
end pmi_pll_fp;
